october 2012 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN5903 ? rev. 1.0.8 FAN5903 ? buck converter with byp ass mode for 3 g / 3.5 g / 4 g pas provided under nda ? proprietary and confidential ? do not distribute FAN5903 buck converter with bypass mode for 3 g / 3.5 g / 4 g pas features ? 2.7 v to 5.5 v input voltage range ? v out range from 0.4 v to 3.5 v (or v in ) ? small form factor inductor o 2012 470 nh or 540 nh for minimal pcb area o 2520 1.0 h for higher efficiency ? bypass dropout at 500 ma, 60 mv typical ? 100% duty cycle for low dropout operation ? input under-voltage lockout / thermal shutdown ? 1.34 mm x 1.29 mm, 9-bump, 0.4 mm-pitch wlcsp ? 3 mhz / 6 mhz selectable switching frequency to facilitate system optimization ? high-efficiency pfm operation at low power ? sleep mode for very low i q operation ? up to 96% efficient synchronous operation at high-power conditions ? 10 s output voltage step response for early power loop settling applications ? dynamic supply bias for 3g/3.5g and 4g pas ? power supply for wcdma/lte pas resources for more information or a fu ll copy of this datasheet, please contact a fairchild representative. description FAN5903 is a high-efficiency, low-noise, synchronous, step-down, dc-dc converter designed for powering 3 g / 3.5 g / 4 g rf power amplifiers (pas) in handsets and other mobile applications. the output voltage may be dynamically varied from 0.40 v to 3.50 v, proportional to an analog input v con , ranging from 0.16 v to 1.40 v provided by an external dac. this allows the pa to be supplied with the voltage that enables maximum power-added efficiency. an integrated bypass fet aut omatically switches on when battery voltage drops close to the desired output voltage (v out =v bat -200 mv). the dc-dc switches back to synchronous mode when the voltage dropout exceeds 375 mv. the integrated bypass fet is also enabled when v con is nominally greater than to 1.5 v. the FAN5903 offers fast transition times, enabling changes to the output voltage in less than 10 s for power transitions. moreover, a current-mode control loop with fast transient res ponse ensures excellent line and load regulation. light-load efficiency is optimized by operating in pfm mode for load currents typically less than 100 ma. the switching frequency may be set to 3 mhz or 6 mhz, enabling further optimization of system performance. the FAN5903 typically uses a single, small-form-factor inductor of 540 nh. efficiency may be further optimized using a 1.0 h inductor when running at 3 mhz. when output regulation is not required, the FAN5903 may be placed in sleep mode by setting v con nominally to 50 mv. this ensures a very low i q (<70 a) while enabling a fast return to output regulation. the FAN5903 enables significant current reduction and increased talk time and is available in a 1.34 mm x 1.29 mm, 9-bump, 0.40 mm-pitch, wlcsp package. ordering information part number operating temperature range package packing method FAN5903ucx -40 to +85c 1.34 mm x 1.29 mm, 9-bump, 0.4 mm pitch, wafer-level chip-scale package (wlcsp) tape and reel
provided under nda ? proprietary and confidential ? do not distribute ? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN5903 ? rev. 1.0.8 18 FAN5903 ? buck converter with bypass mode for 3 g / 3.5 g / 4 g pas physical dimensions product d e x y unit FAN5903ucx 1.292 0.030 1.342 0.030 0.271 0.246 mm figure 42. 1.34 x 1.29mm, 9- bump, 0.4mm-pitch wlcsp package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. 0.03 c 2x b a 0.03 c 2x 0.2080.021 0.2920.018 d c 0.06 c 0.05 c pin a1 index area notes: a. no jedec registration applies. b. dimensions are in millimeters. c. dimensions and tolerance per asmey14.5m, 1994. d. datum c is defined by the spherical crowns of the balls. e. package nominal height is 500 microns 39 microns (461-539 microns). f. for dimensions d, e, x, and y see product datasheet. g. drawing filname: mkt-uc009aerev1 f f e e d a1 ?0.20 cu pad ?0.30 solder mask 0.40 0.40 side views ?0.2600.020 9x 0.40 0.40 (x)0.018 (y)0.018 a b c 123 bottom view top view 0.539 0.461 seating plane land pattern recommendation (nsmd pad type)
provided under nda ? proprietary and confidential ? do not distribute ? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN5903 ? rev. 1.0.8 19 FAN5903 ? buck converter with bypass mode for 3 g / 3.5 g / 4 g pas
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